1. Field of the Invention
The present invention relates to a nonvolatile memory and a manufacturing method thereof.
2. Description of the Related Art
The cost of a NAND flash memory can be most effectively reduced by achieving finer patterning and thereby increasing the chip yield per wafer, or by increasing the number of memory cells per unit area and thereby increasing the capacity.
If, however, the NAND cells that store charge in their floating gates (FGs) are simply made smaller, the spacing between active areas (AA) and between the floating gates of adjacent memory cells is reduced. This would increase interference between cells (see Jpn. PCT National Publication No. 2005-530362). In other words, the FGs of adjacent memory cells are arranged closer as the patterning becomes finer. Then, the charge accumulated in the FGs causes a leakage field and changes the threshold voltage of the cell transistor, which results in a read error.
In MONOS and MNOS memories, in which charge is uniformly distributed, the center of charge serves as the center of the cell. Each cell can therefore be separated from the charge for a distance equivalent to half the width of the AA or FG. However, as the packing density increases, the same read-error problem arises.
For this reason, a memory cell structure of a nonvolatile memory and method thereof, with which interference between cells can be suppressed, have been sought.